Priority is claimed to Japanese Patent Application Number JP2005-356008 filed on Dec. 9, 2005, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device which realizes reduction in a device size while maintaining breakdown voltage characteristics thereof, and a method of manufacturing the same.
2. Description of the Prior Art
As an example of a conventional semiconductor device, a structure of the following NPN transistor 61 has been known. As shown in FIG. 9, an N type epitaxial layer 63 is formed on a P type semiconductor substrate 62. In the epitaxial layer 63, P type buried diffusion layers 64 and 65, which expand vertically (in a depth direction) from a surface of the substrate 62, and P type diffusion layers 66 and 67, which expand from a surface of the epitaxial layer 63, are formed. Moreover, the epitaxial layer 63 is divided into a plurality of element formation regions by isolation regions 68 and 69 which are formed by connecting the P type buried diffusion layers 64 and 65 with the P type diffusion layers 66 and 67, respectively. In one of the element formation regions, for example, the NPN transistor 61 is formed. The NPN transistor 61 is mainly configured of: an N type buried diffusion layer 70 and an N type diffusion layer 71, which are used as a collector region; a P type diffusion layer 72 used as a base region; and an N type diffusion layer 73 used as an emitter region. This technology is described for instance in Japanese Patent Application Publication No. Hei 9 (1997)-283646 (Pages 3, 4 and 6, FIGS. 1 and 5 to 7).
As described above, in the conventional semiconductor device, the epitaxial layer 63 is formed on the semiconductor substrate 62. In the epitaxial layer 63 divided by the isolation regions 68 and 69, the NPN transistor 61 is formed. The epitaxial layer 63 is an N type low impurity concentration region. By use of this structure, when a formation region of the P type buried diffusion layer 64 or the P type diffusion layer 72 is shifted, a distance L2 between the both diffusion layers 64 and 72 is shortened to narrow a region for a depletion layer to spread. Moreover, in the NPN transistor 61, a short-circuit is likely to occur between the base region and the isolation region. As a result, there is a problem that it is difficult to achieve desired breakdown voltage characteristics. Moreover, there is a problem that a variation in the distance L2 destabilizes the breakdown voltage characteristics of the NPN transistor 61.
Moreover, in the conventional semiconductor device, a thickness of the epitaxial layer 63 is determined by taking account of a breakdown voltage of the NPN transistor 61 and the like. For example, in a case where a power semiconductor element and a control semiconductor element are monolithically formed on the same semiconductor substrate 62, the thickness of the epitaxial layer 63 is determined depending on breakdown voltage characteristics of the power semiconductor element. Moreover, the P type buried diffusion layers 64 and 65, which respectively form the isolation regions 68 and 69 expand upward from the surface of the substrate 62 toward the epitaxial layer 63. Meanwhile, the P type diffusion layers 66 and 67, which respectively form the isolation regions 68 and 69 expand downward from the surface of the epitaxial layer 63. By use of this structure, lateral expansion widths W4 and W5 respectively of the P type buried diffusion layers 64 and 65 are also increased depending on the expansion widths thereof. In order to realize a desired breakdown voltage of the NPN transistor 61, the distance L2 between the P type diffusion layer 72 and the P type buried diffusion layer 64 which forms the isolation region 68 is required to be a certain distance or more. As a result, there is a problem that the increase in the lateral expansion widths W4 and W5 of the P type buried diffusion layers 64 and 65 makes it difficult to reduce the device size of the NPN transistor 61.